Back in the 1980s and 1990s, latch-up was a huge concern for the semiconductor world. The original test procedure for latch-up “JEDEC-17 Latch-Up in CMOS Circuits” was published in 1988 and replaced in 1998 by IEC/JEST-78 which was updated multiple times to revision E. These procedures enabled manufacturers to get a handle on the problem and get the situation under control.
As a supplier of the MultiTrace, we were very active in the development of software running on the MultiTrace to support the Static I-Test and the VDD OverVoltage test. We also took part in the working group for Transient latch-up and developed prototype hardware and procedures. Through data generated by the MultiTrace and other vendor’s hardware, manufacturers could eventually develop design rules that largely avoided latch-up so it’s not considered a major concern anymore.
Moving to the present day, semiconductor companies have focused on lower power designs and scaled-down feature sizes. Both directions resulted in new, smaller device features that had become more sensitive to latch-up. This fueled a more recent round of testing and development. Device scaling to smaller feature size and lower power designs are still a focus of most semiconductor products and latch-up remains a concern justifying continued testing of new designs to qualify them for shipping.
For most major semiconductor purchasers at OEM companies, Latch-Up testing and characterization is still a requirement for purchase. For medical device manufacturers, it continues to remain a requirement for high reliability. In fact, the Latch-Up test is often applied to technologies that are not CMOS as a matter of standard procedure.
The MultiTrace and MegaTrace have supported static Latch-Up testing for as long as they have existed. Designed from scratch to support latch-up and curve tracing, many features in the measurement system and the high performance of the SMUs in current source mode make this possible. The MultiTrace supports the I-Test, VDD overvoltage test with the purchase of the MTForms Latch-Up version. The software comes bundled with a latch-up report generator and activation of the Data Extraction features in DataTrace.
Data Extraction Tool
Screenshot of an LU Report
“latch-up” refers to a failure mode in which a CMOS device experiences a significant and sustained elevation of the supply current resulting from a voltage spike on one of the device pins. High supply current leads to either temporary functional failure of the device or even permanent Electrical Overstress.
“Latch-Up testing” refers to a systematic test where progressive overvoltage pulses apply to specific pins of the device and the supply currents checked to see if they’re disturbed after the pulse has ended. RTI has detailed application notes you can request if you would like to learn more.
Intended for the reliability engineer, Latch-Up testing is also valuable to the failure analysis engineer. Sometimes it is useful to show on a new device that latch-up is possible in order to show that a failed device was caused by latch-up. The LU failure signature often damages the device severely, making it difficult to see the initiation point. Triggering latch-up in an emission system can lead directly to corroboration of a failure mode and point clearly where corrective action is needed.
diagram of LU parasitic transistors
LU graph on DataTrace or StdTrace
On the MultiTrace, latch-up is data-intensive, unlike some production-oriented test systems. The MultiTrace collects ‘before, during, and after pulse’ supply current data from all supplies powering the device as well as voltage and actual pulse current. A 6-bus MultiTrace can easily configure 2,4 VDD tests and, with some customization, up to 6 supplies. The use of the powered curve trace method while developing test conditions further gives confidence that the resulting data is accurate, and the test conditions are rational. The high correlation between latch-up and powered curve trace makes detailed FA possible and improves the credibility of obtained results.
