In the dynamic landscape of industrial development and technological innovation, semiconductor Failure Analysis (FA) remains a critical process for ensuring the reliability, safety, and efficiency of various components and systems. To date, semiconductor FA has relied on two major capabilities—our ability to access (probe) and observe (image) the internal structures by which complex semiconductor devices operate. Packing more computational power and functionality into individual packages introduces additional levels of complexity and opportunities for failure. Scanning and probing the internal structures of semiconductor devices after die singulation is crucial for identifying and mitigating device failures.

How are test equipment and fixture manufacturers rising to the demand for improving physical and optical access for FA? By following the packaging trends in footprint miniaturization while improving manufacturing tolerances for precise alignment and device access; often using new materials to make the test hardware as ‘invisible’ as possible to the device during test.

To a test engineer, this is clear in the test socket’s increasingly narrow pin pitch and design customization that allows physical access to specific places on the top and backside of the DUT. Robson Technologies, Inc. (RTI) is responding to the tighter lead pitches by working with a variety of pin suppliers in pursuing smaller/shorter pogo pins and other interconnect technologies in their test sockets while expanding the working area surrounding the sample DUT for improved inspection methods and physical device access.

Integration with Advanced Imaging Techniques

Advanced imaging techniques, such as Transmission Electron Microscopy (TEM), Scanning Electron Microscopy (SEM) and X-ray Computed Tomography (CT), provide high-resolution images of failed components. When combined with AI and ML, these techniques can offer unprecedented insights into failure mechanisms at micro and nano scales. We’re already seeing AI algorithms analyze and upscale these images to identify microscopic defects or patterns that contribute to failure, often much more quickly than manual analysis alone. However, capturing these images and feeding AI datasets is still a chore when working towards achieving defect accuracy greater than 98%.

“For the device front-end FA, we expect a growing need for FA tools to provide atomic-level resolution with 3D localization of species of a given volume. (1)” With chip scale packaging, RTI saw an increase in demand for quartz and sapphire glass window lids to provide total visibility of the WLCSP device during inspection. Now as the line between packaged, chip-scale, and die-level devices blurs, even a thin layer of sapphire glass between the lens and the DUT is prohibitive. To achieve higher levels of optical resolution, high-numerical-aperture (NA) objectives, such as Solid Immersion Lenses (SILs), must contact the physical die to scan narrow areas of the subsurface materials.

From a test engineer’s standpoint, contacting the die requires ample space for the lens to extend beyond the exposed die. Sometimes, to prevent SIL obstruction, we need to isolate the die and position it higher on the z-axis plane than the surrounding components. To address this, some OEMs have turned to using ‘coupon boards’ which act as an interposer layer between the DUT and the pogo pin contacts on the socket body.

Test socket for coupon board gives unimpeded access to area around DUT

Test socket for coupon board gives unimpeded access to area around DUT

If the DUT can be taken off the application board and reflowed onto a coupon carrier board, this approach allows for the highest level of surface access at the die level, akin to pre-diced wafer inspection. The coupon board also serves to mount the device to the socket and prevent any force applying to the exposed die itself.

Gaining access to buried layers for fault isolation

The intricate package architecture found in advanced 2.5D and 3D heterogeneous packages presents a considerable obstacle to traditional fault isolation using conventional Thermal Emission (TEM) or probing methods. Internal die-to-die interconnects using Thru Silicon Vias (TSVs) rarely share a direct connection to external BGA balls or package leads for electrical stimulation. This is clear in stacked die devices where memory modules directly installed onto the processor. There are no bridge dies or extended redistribution layers (RDLs) available between the two layers for routing out signals to test points for probing.

Since the late 1990s, a fault isolation method called magnetic field imaging (MFI) has allowed for the detection of deeply buried currents within a suspect device. MFI relies on sensing the magnetic field generated by even the weakest signals within the device. These fields can pass through most materials used in device packaging without interference, although they are impacted by some materials used in off-the-shelf test sockets.

The materials used in custom test sockets must consider the test environment if they are to operate reliably. To aid in MFI screening, RTI offers precision machined test sockets that use high performance, non-magnetic materials to prevent EMF interference. These sockets typically use standard gold plated BeCu pogo pins with austenitic stainless-steel springs and assembly hardware such as brass, aluminum, and nylon to remain ‘invisible’ during test.

Aluminum alignment and nylon screws used in non-magnetic test sockets

Aluminum alignment and nylon screws used in non-magnetic test sockets

Besides magnetic interference, sockets and DUT board materials must be able to handle varying degrees of heat or moisture in the test environment to mitigate the socket or DUT warping during test. To achieve higher resolution imaging in smaller regions, it is crucial that sockets and DUT board materials do not contribute to vibration or allow for migration/movement of the DUT during test. Sourcing complete test interface solutions from a single manufacturer like RTI can ensure precise alignment and interoperability between all components in the hardware stack up throughout hours of imaging.

The Role of Big Data in Failure Analysis

The surge of big data technologies has provided a fertile ground for AI and ML to thrive in the realm of failure analysis. The ability to collect, store, and process large volumes of data from a variety of sources–including sensors, maintenance logs, and operation records–has significantly enhanced the predictive capabilities of AI models. By employing Federated Learning, individual researchers can contribute to a larger AI model without sharing their raw data with other labs or companies that use the same fundamental model. The big data approach allows labs to understand failure mechanisms holistically, taking into account different factors without the need to disclose their proprietary datasets.

The ability to configure, collect, and export test data rapidly in both graphical and numeric formats for training AI models is a key feature of RTI’s MultiTrace automated curve tracer. This early-stage diagnostic test tool detects low-level leakage in failing devices using low input voltages. It offers a straightforward workflow and generates high-resolution I-V curve tracing results, which users can catalog for immediate report generation and long-term machine learning.

Curve Tracing results in numeric and graph formats for AI datasets

Curve Tracing results in numeric and graph formats for AI datasets

Automated curve tracing software provides a variety of electrical test methods to further isolate potential failure points within complex and high pin count packages when used with emission microscopy, X-ray, and other non-invasive laser probing screening tools. RTI recognizes it is the manufacturer’s responsibility to share the safe operational procedures for maximizing the tool’s effectiveness and reliability. That’s why a remote engineer is available to provide operator training and support all hardware and software tools. With the help of knowledgeable on-site tool owners, we can quickly resolve service and support issues online to maximize service uptime.

Creating semi-custom solutions for novel testing challenges

Since the dawn of civilization, we have created tools that helped us create better tools. To do this, we identify how and why the current generation of the tool fails. In the semiconductor industry, understanding why chips and systems fail under certain conditions is crucial for continuous improvement and risk mitigation.

To gain this understanding, semiconductor failure analysts must be able to determine the root cause failure by observing and accessing the physical structures within the DUT. In order to gain access to these fragile microscopic structures for observation, standardized sample preparation and test processes coupled with reliable semi-custom hardware test interfaces are required.

All DUTs undergoing FA must have isolated access to a hardware interface that powers specific regions of the device and aligns it with inspection tools for identifying failure causes. Companies such as RTI play a pivotal role in designing and manufacturing test-ready hardware and software tools that address the need for electrical, physical, and optical access to facilitate front-end fault isolation and root-cause failure analysis workflows. Working with a knowledgeable test solutions provider like RTI prepares you for success in the complex world of semiconductor failure analysis.

 

(1) https://doi.org/10.31399/asm.tb.edfatr.t56090155 (c) 2023 ASM International